DS1004Z-5+T【PDF 5/6 页】IC DELAY LINE 5TAP 25NS 8-SOIC

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Sheet目录1992

1页 2页 3页 4页 [5页]6页

DS1004

5 of 6

NOTES:

1. All voltages are referenced to ground.

2. VCC=5V and 25

°C. Delay accuracy on both the rising and falling edges within tolerances given in

Table 1.

3. Pulse width and duty cycle specifications may be exceeded, however, accuracy will be application

sensitive with respect to decoupling, layout, etc.

TEST CONDITIONS

INPUT:

Ambient Temperature:

°C ±=3°C

Supply Voltage (VCC):

5.0V

±=0.1V

Input Pulse:

High = 3.0V

±=0.1V

Low = 0.0V

±=0.1V

Source Impedance:

50 ohm max.

Rise and Fall Time:

3.0 ns max. (measured between 0.6V and 2.4V)

Pulse Width:

500 ns

Pulse Period:

Output Load

Capacitance:

15 pF

OUTPUT:

Each output is loaded with the equivalent of one 74F04 input gate. Data is measured at the 1.5V level on

the rising and falling edge.

NOTE:

Above conditions are for test only and do not restrict the devices under other data sheet conditions.

TIMING DIAGRAM: DS1004 INPUT TO OUTPUTS

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